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| data sheet , rev. 1.1 , jan. 2009 tle 7241e dual channel constant current control solenoid driver automotive power
data sheet 2 rev. 1.1, 2009-01-19 tle 7241e table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 functional description and electrical characteristics . . . . . . . . . . . . 13 5.1 supply and reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 power output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 protection and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 overvoltage sensing and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 overcurrent / short to v bat sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.3 open load / short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.4 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.1 hysteretic current cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.2 dither control and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5.3 input command out of range / dither clipping . . . . . . . . . . . . . . . . . . 43 5.5.4 error correction registers / average sw itch threshold trimming . . . . 44 5.6 spi command and diagnosis structure . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.2 spi command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1 layout notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table of contents dual channel constant current control solenoid driver tle 7241e data sheet 3 rev. 1.1, 2009-01-19 type ordering code package tle 7241e on request pg-dso-20-27 1overview 1.1 features ? two fully independent channels ? integrated n-channel dmos transistors ? programmable average current with 10-bit resolution via spi ? i avg range = 0 to 1000 ma (typical) ? programmable superimposed dither ? programmable frequency (41 hz to 1 khz typ) ? programmable amplitude (12.5 to 390 mvpp typ) ? programmable hysteresis (40 to 110 mvpp typ) ? interface and control ? 16-bit spi (serial peripheral interface) daisy chainable ? a single ?default? pin to disable both channels and reset the programmable registers of both channels ? 5.0 v and 3.3 v logic compatible i/o ? the contents of all registers can be verified via spi ? operation with or without external reference possible ? protection ? overcurrent ?overvoltage ? overtemperature ? diagnostics ? overcurrent / shorted solenoid ? overtemperature ? open load ? short to gnd ? green product (rohs compliant) ? aec qualified pg-dso-20-27 data sheet 4 rev. 1.1, 2009-01-19 tle 7241e overview 1.2 applications ? variable force solenoids (e.g. automatic transmission solenoids) ? constant current controlled solenoids like ? idle speed control ? exhaust gas recirculation ? valve control ? suspension control 1.3 general description the tle 7241e is a dual channel constant current control solenoid driver with integrated dmos power transistors. the average load cu rrent can be programmed to a value in the range of 0 ma to 1000 ma (with a 1 external sense resistor) wit h 10 bits of resolution. load current is controlled using a hyster etic control scheme with a programmable hysteresis value. a triangular ?dither? wa veform can be superim posed on the switching current waveform in order to improve the tran sfer function of the solenoid. the amplitude and frequency of the dither waveform are programmable by the spi interface. the device is protected from damage due to ov ercurrent, overvoltage and overtemperature conditions, and is able to diagnose and r eport open loads, shorted loads, and loads shorted to ground. note: an external free-wheeling diode must be provided when using the tle 7241e in constant current cont rol mode, otherwise the ic will be damaged. for best accuracy, an external 2.5 v reference voltage should be supplied at the ref pin. the tle 7241e also includes an internal 2.5 v reference voltage, which can be selected by connecting the ref pin to ground . the reference voltage selection (internal or external) can be verified via the spi interface. tle 7241e overview data sheet 5 rev. 1.1, 2009-01-19 application block diagram bat pgnd2 neg1 out1 pos1 logic spi channel 2 channel 1 vso si so sck vdd ref neg2 out2 pos2 bat ref csb vbat so lenoid vbat vbat so len oid default vbat test pgnd1 gnd figure 1 basic application diagram data sheet 6 rev. 1.1, 2009-01-19 tle 7241e overview detailed block diagram pos1 out1 neg1 spi interface + - logic and gate drive with overload protection diff amp diagnostics & protection * over temp * open load while on * open load while of f * shorted load * load short ed t o ground * overvolt age (vpwr) register bank control circuit dither register aver age curr ent slew rate status switching hysteresis fault type bit error cor reg 200mv error cor reg 400mv error cor reg 600mv error cor reg 800mv error cor reg 1000mv revision code int vref dither osc vbat channel #1 channel #2 csb sck si so vso pos2 out2 neg2 default spi decoder vdd ref bat gnd vso vcal detect tem p vref vdd vdd test pgnd2 pgnd1 14 6 16 4 3 2 1 17 18 19 20 15 12 10 8 9 11 13 7 figure 2 detailed block diagram tle 7241e pin configuration data sheet 7 rev. 1.1, 2009-01-19 2 pin configuration pin assignment pinout.vsd tle 7241e pgnd1 out1 pos1 neg1 pgnd2 out2 pos2 neg2 bat gnd sck vdd csb si ref test default so vso n.c. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 epgnd figure 3pin-out pin definitions and functions pin pin name pin description 1 pgnd1 power ground channel 1; internally connected to pgnd2 2 out1 output channel 1 ; drain of output dmos; connect to negative terminal of external sense resistor 3 neg1 negative sense pin channel 1 ; connect to negative terminal of external sense resistor with dedicated trace 4 pos1 positive sense pin channel 1 ; connect to positive terminal of external sense resistor with dedicated trace 5 nc not connected; not bonded internally 6 v dd logic supply voltage; connect a ceramic capacitor to gnd near the device 7 default control input; active high digital input. 3.3v and 5.0v logic compatible. in case of not used, connect to ground data sheet 8 rev. 1.1, 2009-01-19 tle 7241e pin configuration note: if a channel is unused, the outx, negx, and posx pins should be connected together. 8 sck spi clock ; digital input pin. 3.3v and 5.0v logic compatible 9 csb chip select bar ; active low digital input pin. 3.3v and 5.0v logic compatible 10 si serial data input; 3.3v and 5.0v logic compatible 11 v so spi supply voltage; connect a ceramic capacitor to gnd near the device 12 so serial data output ; supplied by vso pin 13 test test pin; connect to gnd 14 ref voltage reference; connect to external 2.5 v reference, or connect to gnd to enable internal reference. 15 gnd ground ; signal ground 16 bat bat input; connect to the solenoid supply voltage through a series resistor. co nnect a ceramic capacitor to gnd near the device 17 pos2 positive sense pin channel 2 ; connect to positive terminal of external sense resistor with dedicated trace 18 neg2 negative sense pin channel 2 ; connect to negative terminal of external sense resistor with dedicated trace 19 out2 output channel 2 ; drain of output dmos; connect to negative terminal of external sense resistor 20 pgnd2 power ground channel 2; internally connected to pgnd1 expose d lead frame epgnd gnd; should be connected to gnd, pgnd1 and pgnd2 and to the ground plane of the ecu pin definitions and functions (cont?d) pin pin name pin description tle 7241e maximum ratings data sheet 9 rev. 1.1, 2009-01-19 3 maximum ratings absolute maximum ratings 1) t j = -40 to 150 c pos. parameter symbol limit values unit notes min. max. voltages m.1 supply voltage bat v dd v so -0.3 -0.3 -0.3 50 6.0 6.0 vdc vdc vdc ? m.2 analog input voltage posx negx posx-negx -0.3 -0.3 -0.3 50 50 20 vdc vdc vdc ? m.3 output voltage outx -0.3 50 vdc ? m.4 digital input voltage ref test si sck csb default -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 min. (6.0, v dd + 0.3) 6.0 6.0 6.0 min. (6.0, v so + 0.3) min. (6.0, v so + 0.3) vdc vdc vdc vdc vdc vdc ? m.5 digital output pin voltage so -0.3 min. (6.0, v so + 0.3) vdc ? m.6 dynamic clamp voltage t clamp < 2.0 ms bat posx negx outx -1.5 -1.5 -1.5 -1.5 ? ? ? ? v v v v ? m.7 ground pin voltage (gnd) gnd -0.3 0.3 vdc ? m.8 difference between pgnd1 and pgnd2 pgndx -0.3 0.3 vdc ? others m.9 biased junction temperature t j -40 150 c ? m.10 storage temperature t st -55 150 c ? m.11 single clamp energy (outx) i=1.0a tj=150 c e max ? 30 mj ? data sheet 10 rev. 1.1, 2009-01-19 tle 7241e maximum ratings all voltages are with respect to pgnd1 & 2. positive current flow s into the pin unless otherwise specified. attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. m.12 esd hbm all pins eia/jesd22-a 114b (1.5 k , 100 pf) ? -2 +2 kv ? m.13 esd mm all pins eia/jesd22-a115a (0 , 200 pf) ? -200 200 v ? 1) not subject to production test, specified by design absolute maximum ratings 1) (cont?d) t j = -40 to 150 c pos. parameter symbol lim it values unit notes min. max. tle 7241e functional range data sheet 11 rev. 1.1, 2009-01-19 4 functional range t j = -40 to 150 q c; v ref = 2.5v pos. parameter symbol limit values unit remarks min. max. f.1 voltage at bat v bat 9 18 v ? f.2 voltage at v dd v dd 4.75 5.25 v ? f.3 voltage at vso v vso 3.1 v dd + 0.3 or 5.25v v ? f.4 voltage at si, sck v in1 -0.3 v dd + 0.3 v ? f.5 voltage at csb, default, so v in2 -0.3 v so + 0.3 v ? f.6 voltage at pos1, pos2, neg1, neg2, out1, out2 v out , v pos , v neg -0.3 50 v ? f.7 voltage difference pos1-neg1, pos2-neg2 v pos - v neg 0 1.23 v ? f.8 voltage at pgnd1, pgnd2, gnd v gnd -0.3 0.3 v ? f.9 spi clock frequency f clk 3.2 mhz c so = 200 pf max; v vso = 5 v f.10 junction temperature t j -40 150 q c ? note: within the functional range the ic o perates as described in the circuit description. the electrical charac teristics are specified within the conditions given in the related electrical charac teristics table. 4.1 thermal resistance pos. parameter symbol limit values unit conditions min. typ. max. g.1 junction to case 1) r thjc 5.2 k/w 2) g.2 junction to ambient 1) r thja 26 k/w 2) 3) functional range data sheet 12 rev. 1.1, 2009-01-19 tle 7241e functional range 1) not subject to production test, specified by design. 2) both channels on with 1w power dissipation per channel 3) specified rthja value is according to jedec jesd51-2, -5, -7 at natura l convection on fr4 2s2p board. the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70mm cu, 2 x 35 mm cu). where applicable a the rmal via array under the exposed pad contacted the first inner layer. tle 7241e functional description and electrical characteristics data sheet 13 rev. 1.1, 2009-01-19 5 functional description and electrical characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify me an values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 q c and the given supply voltage. 5.1 supply and reference the device has incorporated a power-on reset circuit. this feature will reset the commanded average current to 0 ma (device off), and will reset the programmable registers to their default values. the fault re gister bits are reset during power on reset. the device will remain off until a valid command is received. the device will also be reset in the case of an undervoltage condition on the pin v dd . note that if the voltage on the pin ref pin is greater than the voltage on the pin v dd, a current will flow from the ref pin to the v dd pin. t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) target @ t j = 25 q c typ. 2) ref bias current i ref -20 ? 20 p a v ref = 2.5 v (includes leakage current and a small current sink) v dd 5 v supply current i dd ? ? 15 ma v dd = 5.25 v; csb = 5.0 v; dac = 3ff v so i/o supply current i so ? ? 1 ma v so = 5.25 v; csb = 5.0 v bat supply current i bat ? ? 1 ma v dd = 5.25 v; csb = 5.0 v v dd power-on reset threshold v por 2.5 ? 3.5 v power-on reset threshold internal reference voltage v iref 2.45 2.5 2.55 v tested at wafer test. electrical char acteristics 1) 1) positive current flow is into the device. max. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 data sheet 14 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.2 input/output the default pin is an active high input. a weak pull-up current (typical 15 p a) on this pin ensures a defined level when this pin is not connected (e.g. open pin). an active high signal on the default pin sets the comm anded current for both channels to 0 ma, and resets all programmable registers to their default values. any spi commands that are received while the default pin is high will be ignored, and the so pin will remain in a high impedance state. the fault register bits are not cleared when the default pin is asserted. upon coming out of default mode, the commanded current will remain at 0 ma, device off, and the programmable registers w ill remain at their default values. the default pin must be asserted high whenever the voltage on the pin v dd is less than the minimum v dd operating voltage (4.75 v), otherwi se the electrical characteristic specifications (see table below) may not be met. the diagnostic functions are not operational when the v dd voltage is less than 4.75v. the test pin is an active high pin. this pi n must be connected directly to ground in the application, as it is only used for ic test purposes. a passive pull-down resistor in the device ensures a logic low value when the pin is not connected. t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) target @ t j = 25 q c typ. 2) default input bias current i default -25 -10 -5 p a v default = 0 v; pull-up source is pin v so test pull-down resistor r test ? 20 ? k : ? si, sck, csb, default input threshold v ih 2.0 ? ? v sck is specified by design, not subject to production test. si, sck, csb, default input threshold v il ? ? 0.8 v sck is specified by design, not subject to production test. so output high voltage v oh 0.8 v so ? ? v so i o = -1 ma so output low voltage v ol ? ? 0.4 v so i o = 1 ma electrical char acteristics 1) 1) positive current flow is into the device. max. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 tle 7241e functional description and electrical characteristics data sheet 15 rev. 1.1, 2009-01-19 5.3 power output the slew rate of the voltage on the pins ou t1 and out2 are programmable via the spi interface. the fast settings are intended for fa st switching solenoids (low inductance) to minimize power dissipation within the tle 7241e, and to minimize dc current error due to overshooting the switch points. the slower slew rates can be used with slower switching solenoids (high inductance) to improve radiated emissions from the wiring harness. t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) t j = 25 q c typ. 2) outx rise and fall times slew rate reg = 0 outx t r and t f 0.25 0.5 1 p s threshold: 4 v to 10 v v bat = 14 v; r load = 5 : outx rise and fall times slew rate reg = 1 outx t r and t f 0.5 1 2 p s threshold: 4 v to 10 v v bat = 14 v; r load = 5 : outx rise and fall times slew rate reg = 2 outx t r and t f 1 2 4 p s threshold: 4 v to 10 v v bat = 14 v; r load = 5 : outx rise and fall times slew rate reg = 3 outx t r and t f 2.5 5 10 p s threshold: 4 v to 10 v v bat = 14 v; r load = 5 : outx output off leakage (00 h ) i dss ? ? 10 p a v ds = 24 v outx output off leakage (00 h ) i dss ? ? 3 ma v ds = v clamp - 1v v clamp is the measured clamp voltage ( item 5.4.1.3 ) 3) electrical distributions must be performed on this parameter as defined in the aec-q100 specification table 2 test 27. outx 3) driver on resistance r ds(on) ? 240 450 m : driver on resistance @ t j = 150 q c electrical char acteristics 1) 1) positive current flow is into the device. max. 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 data sheet 16 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.4 protection and control t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) t j = 25 q c typ. 2) pos/neg ibias pos/neg ibias -500 ? 500 p a dac command =3ff pos=neg=0v & pos=neg=17v pos/neg leakage pos/neg leakage 20 -20 40 0 60 20 p a p a fault typing bit = 0, zero current, pos = neg = 14 v fault typing bit = 1, zero current, pos = neg = 14 v note: integrated protection functions are desi gned to prevent ic destruction under fault conditions described in the data sheet. fa ult conditions are considered as outside normal operating range. protections func tions are not designed for continuous repetitive operation. 5.4.1 overvoltage sensing and protection when the voltage on the bat pin exceeds th e overvoltage shutdown threshold (see table below, item 5.4.1.1 ), the output channel will shut off to protect the ic from excessive power dissipation. a short filter with a typical value of 6.5 p s is included to prevent undesired shutdown due to short transient voltage spikes. although spi communication will remain functional, the output will remain off. the device will resume normal operation when the bat voltage has dropped below the overvoltage hysteresis level. note that the programmable regist ers are not reset, and the dither counter continues to operate dur ing an overvoltage event. both channels are disabled when an overvoltage condition is detected. electrical char acteristics 1) 1) positive current flow is into the device. max. 5.4.1 5.4.2 v posx - v neg x ls-switch state of f on vpwr 14 v vov over-voltage fault t < tov vov-ovhyst tle 7241e functional description and electrical characteristics data sheet 17 rev. 1.1, 2009-01-19 figure 4 overvoltage shutdown t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) t j = 25 q c typ. 2) bat overvoltage shutdown ov 30 35 40 vdc ramp up bat until outputs off bat overvoltage hysteresis ov hyst ? 1.0 ? vdc ramp bat down until outputs on 3) not subject to production test, specified by design. outx active clamp voltage v clamp 50 53 60 v i d = 20 ma, output off 3) 5.4.2 overcurrent / short to v bat sensing an overcurrent fault is detected by sens ing the voltage at the pos input pin. a comparator is used to detect the voltage wh ile the gate drive is on. when the voltage at the pos input pin exceeds the short circuit / overcurrent threshold (see table below, item 5.4.2.3 ) for a time greater than the short sense time (see table below, item 5.4.2.1 ) electrical char acteristics 1) 1) positive current flow is into the device. max. 5.4.1.1 5.4.1.2 5.4.1.3 data sheet 18 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics the driver will be turned off and the overcurrent / short to v bat ( v sht ) fault bit will be latched until the fault register is read via spi. the driver will remain in the off condition for the short circuit refres h time (see table below, item 5.4.2.2 ). after the refresh time, the driver will automatically turn on again. if the short condition is no longer present, the channel will operate normally. if the short ci rcuit condition persists, the driver will be cycled off after the short sense time once agai n. the refresh time has been chosen for minimal increase in power dissipation during a continuous fault condition. in order to prevent false detection of an overcurrent / short to v bat fault during an ?off to on? transition of the low-side output transis tor, the detection circuit is disabled for a blanking time (see ?electrical characte ristics? on page 31 , item 5.5.1.1 and item 5.5.1.2 ) after the transistor is enabled (see figure 16 and figure 17 ). the output transistor control circuit includes a current limit featur e that will limit the transistor current to a maximum value (see table below, item 5.4.2.4 ) in order to protect the device from excessive current flow. if a new average current command or configuration command is received for a shorted channel while that channel is within the shor t circuit refresh time, the new data will be stored but the channel will remain in the off state until the refresh time expires. the new data will become active when the short circuit condition is released. the overcurrent / short to v bat detection is channel specific. note: an overcurrent / short to vbat fault is not detected if the average current command is <50 ma (with 1 w sense resistor). note: an overcurrent / short to v bat fault is latched until read via the miso return word. v posx - v negx vpos 0v 15v load state ok short to vb a t vshtx latched fault state tss tr ef ls-switch state off on short to vbat fault - occurs & clears while on t < tss csb mosi miso vshtx fault state g.c. cmd g.c. response vsh t=0 g.c. cmd g.c. response vsh t=1 g.c. cmd g.c. response vsh t=1 g.c. cmd g.c. response vsh t=0 the lat che d fault st a t e is sa mpled and st ore d in t he spi t rans mit re gist e r at t he point s marked wit h ? ? . tle 7241e functional description and electrical characteristics data sheet 19 rev. 1.1, 2009-01-19 figure 5short to v bat - channel on vposx load state ok short to vbat vshtx latched fault state tss tref ls-switchx state off on 0v 15v v posx - v negx short to vbat fault while on, then turned off csb mosi miso vshtx fault state g.c. cmd g.c. response vsht=0 g.c. response vsht=1 a.c. c md iav =0ma g.c. cmd g.c. response vsht=1 g.c. response g.c. cmd vsht=0 edg =1 a.c. response g.c. cmd the lat ched fault state is sampled and st ored in the spi transmit register at the point s marked wit h ? ? . figure 6short to v bat - channel on then turned off v posx - v negx vpos 0v 15v load state ok short to vbat vshtx latched fault state tss tref ls-switch state off on sho rt to vbat fault - o ccurs while o ff then turned o n csb mosi miso vshtx fault state g.c. cmd g.c. response vsh t=0 a.c. cmd iav>50ma a.c. response ed g =0 g.c. cmd g.c. response vsh t=1 g.c. cmd g.c. response vsh t=1 g.c. cmd g.c. response vsh t=0 the latched fault state is sampled and stored in the spi transmit register at the points marked with ? ? . data sheet 20 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 7short to v bat - channel off then turned on t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) t j = 25 q c typ. 2) outx short sense time t ss 30 60 90 p s 50 - 50 threshold outx short refresh time t ref 3 14 24 ms 50 - 50 threshold outx short circuit/ overcurrent fault threshold v vshtoct 2.0 2.5 3.0 vdc v ref = 2.5 v outx current limit i dlim 3.0 5.0 6.0 a v bat = 14 v; v dd = 5v; output on electrical char acteristics 1) 1) positive current flow is into the device. max. 5.4.2.1 5.4.2.2 5.4.2.3 5.4.2.4 tle 7241e functional description and electrical characteristics data sheet 21 rev. 1.1, 2009-01-19 5.4.3 open load / short to ground detection the olsg fault bit is set under the following conditions. operating condition #1 the average current comma nd is > 50 ma (with 1 sense resistor) and the low-side driver is on (solenoid current is increasing). the olsg (open load/short to ground) fault bit will be set if the low-side transistor remains on for a time greater than the on state open sense time ( ?electrical characteristics? on page 23 , item 5.4.3.3 ). operating condition #2 the average current comma nd is > 50 ma (with 1 sense resistor) and the low-side driver is off. the olsg fault bit is set if the voltage on the negx pin is less than the neg pin olsg threshold voltage ( ?electrical characteristics? on page 23 , item 5.4.3.6 ) for a time greater than the neg pin olsg delay time ( ?electrical characteristics? on page 23 , item 5.4.3.5 ). operating condition #3 the average current command is < 50 ma (with a 1 sense resistor) and the fault typing bit = 0. the olsg (open load/short to ground) fault bi t will be set if the pos pin voltage is less than the off state open load threshold ( ?electrical characteristics? on page 20 , item 5.4.2.3 ) for longer than the off state open load sense time ( ?electrical characteristics? on page 23 , item 5.4.3.4 ) or the neg pin is less than the neg pin olsg threshold voltage ( ?electrical characteristics? on page 23 , item 5.4.3.6 ) for a time greater than the neg pin olsg delay time ( ?electrical characteristics? on page 23 , item 5.4.3.5 ). a pull-down current ( ?electrical characte ristics? on page 23 , item 5.4.3.1 ) will be activated between the pos pin and ground when the fault typing bit = 0. operating condition #4 the average current command is < 50 ma (with a 1 sense resistor) and the fault typing bit = 1. the olsg fault bit will be set when the volt age on the pin posx is below the off state open load threshold ( ?electrical characte ristics? on page 20 , item 5.4.2.3 ) for the a time greater than t os(off) ( ?electrical characteristics? on page 23 , item 5.4.3.4 ) or the neg pin is less than the neg pin olsg threshold voltage ( ?electrical char acteristics? on page 23 , item 5.4.3.6 ) for a time greater than the neg pin olsg delay time data sheet 22 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics ( ?electrical characte ristics? on page 23 , item 5.4.3.5 ). a pull-up current ( ?electrical characteristics? on page 23 , item 5.4.3.2 ) will be activated between v dd and the pos pin when the fault typing bit = 1. distinguishing between open load and short to ground faults when an open load/short to ground is flag ged, to distinguish between open load and short-to-ground, a general configuration comm and word must be sent three times to the appropriate channel with the fault typing bit set, and the average current must be programmed to zero. check the ol/sg fault bit from the third write. a ?0? signifies open load, ?1? signifies short-to -ground. a short to ground will still be flagged for 0 ma command current. note that setting the fault typing bit under both normal & fault conditions does not change the status of the output or the current flowing. the fault typing bit enables a 40 a pull-up current on the pos pin when high, and enables a 40 a pull-down current on the pos pin when low. t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. pos open detect current i ol 20 40 60 p a fault typing bit = 0, zero current pos load short to ground detect i sg -60 -40 -20 p a fault typing bit = 1, zero current, pos = neg = 2 v outx on-state open sense time ? pos pin t os (on) 6 12 24 ms 50 - 50 threshold 3) not subject to production test, tested by scanpath. 3) outx off-state open sense time ? pos pin t os (off) 30 60 90 p s 50 - 50 threshold 3) negx open load / short to ground filter time ? neg pin t olsg_n (off) 30 60 90 p s ? negx open load / short to ground detection threshold ? neg pin v olsg_n 2.0 2.8 3.6 v ? tle 7241e functional description and electrical characteristics data sheet 23 rev. 1.1, 2009-01-19 electrical char acteristics 1) 5.4.3.1 5.4.3.2 5.4.3.3 5.4.3.4 5.4.3.5 5.4.3.6 1) positive current flow is into the device. 2) t j = 25 q c data sheet 24 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics diagnostics ti ming diagrams v pos - v neg output transistor state off on load state ok open ol/sgx latched fault state tos (on) csb mosi open circuit / short to ground fault - occurs & clears while on miso t < tos (on) ol /sgx fault state g.c. cmd g.c. response olsg=0 g.c. cmd g.c. response olsg=0 g.c. cmd g.c. response olsg=1 g.c. cmd g.c. response olsg=1 g.c. cmd g.c. response olsg=0 the latched fault state is sampled and stored in the spi transmit register at the points marked with ? ? . figure 8 open load / short to ground fault - channel on csb open load / load shorted to ground fault - occurs while on the n channel is turned off mosi miso t os(of f )=60s tos(on) = 12ms v posx - v negx ls-switch x state off on load state ok open ol/sgx fault state ol/sgx latched fault state g.c. cmd g.c. response olsg=0 g.c. cmd g.c. response olsg=1 a.c. cmd ia v =0 m a a.c. response ed g=1 g.c. cmd g.c. response olsg=1 the latched fault state is sampled and stored in the spi transmit register at the points marked with ? ? . figure 9 open load / short to ground - channel on then turned off v posx load state ok open ol/sgx latched fault state tos (off) 2.5v 14v open circuit fault - occurs & clears while off t < tos (off) csb mosi miso dv pos /dt ol /s gx fault state g.c. cmd g.c. response ols g=0 g.c. cmd g.c. response ols g=1 g.c. cmd g.c. response ols g=0 the latched fault s t at e is sam pled and st ored in the s p i t ransm it regist er at the point s m arked wit h ? ? . tle 7241e functional description and electrical characteristics data sheet 25 rev. 1.1, 2009-01-19 figure 10 open load short to ground - channel off d v pos d t ---------------- - i ol i rrecirc ? ? c pos c neg c out ++ ---------------------------------------------------------- - = (1) i ol = open load detection pull down current (5.4.3.1) i rrecirc = reverse leakage current of recirculation diode c pos = external capacitance on the pos pin c neg = external capacitance of the neg pin c out = external capacitance on the out pin v posx load state ok open ol/sgx latched fault state tos (off) 2.5v 14v open circuit fault - occurs while off then turned on csb mosi miso t os(on) = 12ms ol/sgx fault state g. c. cmd g. c. response ols g=0 g. c. cmd g. c. response ols g=1 a.c. cmd iav>50ma g. c. cmd g. c. response ols g=1 edg=1 a.c. response the latched faul t state i s sampl ed and stored in the spi transmit regi ster at the points marked with ? ? . data sheet 26 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 11 open load / short to ground - channel off then turned on v posx load state ok open ol/sgx latched fault state tos (off) 2.5v 14v open circuit fault - occurs while off then open load / short to groun d test is performed csb mosi miso ol/s gx fault state dv pos /dt g.c. cmd g.c. response ols g=0 g.c. cmd g.c. response ols g=1 g.c. response ols g=1 g.c. response ols g=0 g.c. response ols g=1 tos (off) tos (off) the lat che d fault s t a t e is sa m ple d and s t ored in t he s p i t rans m it regis t e r at t he point s m a rke d wit h ? ? . g.c. cmd ft=1 g.c. cmd ft=1 g.c. cmd ft=1 tle 7241e functional description and electrical characteristics data sheet 27 rev. 1.1, 2009-01-19 figure 12 open load - fault type bit = 1 test d v pos d t ---------------- - i sg i rrecirc ? ? c pos c neg c out ++ ---------------------------------------------------------- - = (2) i sg = short to ground detection pull up current (5.4.3.2) i rrecirc = reverse leakage current of recirculation diode c pos = external capacitance on the pos pin c neg = external capacitance of the neg pin c out = external capacitance on the out pin v posx load state ok short to gnd ol /s gx latched fault state tos (off) 2.5v 14v short to ground fault - occurs & clears while off t < tos (off) csb mosi miso ol /s gx fault state tos (off) g.c. cmd g.c. response ols g=0 g.c. cmd g.c. response ols g=1 g.c. response ols g=1 g.c. response ols g=1 g.c. response ols g=1 g.c. cmd g.c. response ols g=1 g.c. response ols g=0 g.c. cmd the la t c hed fa ult s t at e is s am pled and st ore d in t he s p i t ransm it re gist e r at t he point s m a rke d wit h ? ? . g.c. cmd ft=1 g.c. cmd ft=1 g.c. cmd ft=1 data sheet 28 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 13 short to ground fault type bit = 1 test 5.4.4 thermal shutdown each output transistor includes an independe nt thermal shutdown circuit. when the temperature of the output transistor exce eds a threshold value (see table below, item 5.4.4.1 ), the output transistor will be turned o ff and a fault bit will be set for the failed channel. the transistor will remain off un til the local transistor temperature has decreased by the thermal hysteresis value (see table below, item 5.4.4.2 ), the output transistor will then turn on again. thermal shutdown faults are channel specific. note: a thermal fault is latched unt il read via the mi so return word. v posx - v negx sensor x temp ot shutdown - ot hyst ot shutdown otmpx latched fault state ls-switch x state off on o ver-temperature fault csb mosi miso otmpx fault state g.c. cmd g.c. response otmp=0 g.c. cmd g.c. response otmp=1 g.c. cmd g.c. response otmp=1 g.c. cmd g.c. response otmp=0 the latched fault state is sampled and stored in the spi transmit register at the points marked with ? ? . tle 7241e functional description and electrical characteristics data sheet 29 rev. 1.1, 2009-01-19 ^ figure 14 overtemperature shutdown with restart t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. 2) t j = 25 q c typ. 2) outx overtemperature shutdown threshold otsd 160 ? 190 q c 3) not subject to production test, specified by design. outx overtemperature hysteresis othys ? 10 ? q c 3) 3) electrical char acteristics 1) 1) positive current flow is into the device. max. 5.4.4.1 5.4.4.2 data sheet 30 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.5 current control 5.5.1 hysteretic current control the tle 7241e device uses a hysteretic control method to regulate the solenoid current. the output transistor is toggled on and off ba sed on the measured value of the solenoid current. the solenoid current is measured at the pins posx and negx which are connected to an external current sense resi stor. the device calculates an upper and lower switch point based on the input co mmands from the microprocessor. the output transistor is turned on until the upper thresh old is reached, and then turned off until the lower threshold is reached. see figure 15 for an example of the solenoid current waveform. in this example, the dither is disabled. the average switch point sp avg upper switch pt lower switch pt + 2 ---------------------------------------------------------------------------------------- - = (3) is determined by the contents of th e average current command register. the relationship is: sp avg register value 2 10 ----------------------------------- - 1230 mv u = (4) the hysteresis value can be programmed to a value from 40 mvpp to 110 mvpp in steps of 10 mvpp. hysteresis upper switch point lower switch point figure 15 output current wa veform - no dither tle 7241e functional description and electrical characteristics data sheet 31 rev. 1.1, 2009-01-19 note that the switching frequency and duty c ycle of the output transis tor are not directly controlled by the tle 7241e device and are dependent on the characteristics of the solenoid (inductance, resistance, etc.) and the solenoid supply voltage. electrical char acteristics 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. 5.5.1.1 outx 3) blanking time 1 (see figure 16 , figure 17 ) t blank1 ? 5 ? s slew rate register = 0 or 1. from enable/disable of lowside output transistor to enabling of v pos comparator. 5.5.1.2 outx 3) blanking time 2 (see figure 16 , figure 17 ) t blank2 ? 15 ? s slew rate register = 2 or 3. from enable/disable of output transistor to enabling of v pos comparator. 5.5.1.3 outx 4)5) d v out = 200 mv i avg register = 0a6 h d v out 200 -5% 200 +5% mv output current i out = 200 ma with r sense = 1.0 ref = 2.5v 5.5.1.4 outx 4) 5) d v out = 400 mv i avg register = 14d h d v out 400 -2.5 % 400 2.5% mv output current i out = 400 ma with r sense = 1.0 ref = 2.5v 5.5.1.5 outx 4)5) d v out = 600 mv i avg register = 1f3 h d v out 600 -2% 600 2% mv output current i out = 600 ma with r sense = 1.0 ref = 2.5v 5.5.1.6 outx 4)5) d v out = 800 mv i avg register = 29a h d v out 800 -2% 800 2% mv output current i out = 800 ma with r sense = 1.0 ref = 2.5v data sheet 32 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.5.1.7 outx 4) 5) d v out = 1000 mv i avg register = 340 h d v out1000 -3% 1000 3% mv output current i out = 1000 ma with r sense = 1.0 ref = 2.5v 5.5.1.8 outx 3)5) switching hysteresis 40 sw hyst. register = 0 dac counts = 17 d v hyst40 29.6 39.6 49.6 mvpp 40 mv programmed setting input command > 200 mv ref = 2.5v 5.5.1.9 outx 3)5) switching hysteresis 50 sw hyst. register = 1 dac counts = 21 d v hyst50 40.4 50.4 60.4 mvpp 50 mv programmed setting input command > 200 mv ref = 2.5v 5.5.1.10 outx 3)5) switching hysteresis 60 sw hyst. register = 2 dac counts = 25 d v hyst60 50.1 60.1 70.1 mvpp 60 mv programmed setting input command > 200 mv ref = 2.5v electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. tle 7241e functional description and electrical characteristics data sheet 33 rev. 1.1, 2009-01-19 5.5.1.11 outx 3)5) switching hysteresis 70 sw hyst. register = 3 dac counts = 29 d v hyst70 59.7 69.7 79.7 mvpp 70 mv programmed setting input command > 200 mv ref = 2.5v 5.5.1.12 outx 3)5) switching hysteresis 80 sw hyst. register = 4 dac counts = 33 d v hyst80 70.5 80.5 90.5 mvpp 80 mv programmed setting input command > 200 mv ref = 2.5v 5.5.1.13 outx 3)5) switching hysteresis 90 sw hyst. register = 5 dac counts = 37 d v hyst90 80.1 90.1 101.1 mvpp 90 mv programmed setting input command > 200 mv ref = 2.5v electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. data sheet 34 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.5.1.14 outx 3)5) switching hysteresis 100 sw hyst. register = 6 dac counts = 42 d v hyst100 88.7 99.7 109.7 mvpp 100 mv programmed setting input command > 200 mv ref = 2.5v 5.5.1.15 outx 3)5) switching hysteresis 110 sw hyst. register = 7 dac counts = 46 d v hyst110 100.5 110.5 120.5 mvpp 110 mv programmed setting input command > 200 mv ref = 2.5v 1) positive current flow is into the device. 2) t j = 25 c 3) not subject to production test, specified by design. 4) electrical distributions must be performed on this pa rameter as defined in the aec-q100 specification table 2 test 27. 5) when the internal reference is used (ref pin grounde d), the minimum and maximum limits must be increased by +/- 2% electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. tle 7241e functional description and electrical characteristics data sheet 35 rev. 1.1, 2009-01-19 figure 16 blanking time (output transistor turning off) data sheet 36 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 17 blanking time (output transistor turning on) tle 7241e functional description and electrical characteristics data sheet 37 rev. 1.1, 2009-01-19 5.5.2 dither control and operation the dither waveform is gener ated digitally within the tle 7241e by periodically adding or subtracting from the average cu rrent command regi ster contents. figure 18 is an illustration of the dither waveform. dither amplitude dither period figure 18 dither waveform the dither frequency can be programmed over a range of 41 hz to 1 khz. the dither amplitude can be programmed over a range from 12.5 mvpp to 390 mvpp. the dither waveform can be disabled by cl earing both the dither amplitude and dither frequency fields in the dither configuration register. note: programming the dither frequency field to zero when the dither amplitude is programmed to a non-zero value will re sult in incorrect current regulation. in some applications, an enhanced dither wa veform is required. the enhanced dither waveform will hold the lower switch point at the minimum value (lowest lower switch point within the dither period) until the solenoid current crosses t he lower switch point. this mode may be useful when the decay time of th e solenoid current is slower than the slope of the dither waveform. see figure 19 for an illustration of the enhanced dither waveform. enhanced dither can be enabled by setting a bit in the spi dither configuration word. data sheet 38 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 19 enhanced dither waveform when the enhanced dither bit is selected, t he dither period will only be extended if the lower switch threshold is not crossed during the entire negative slope portion of the dither waveform. example see figure 20 . the first dither period is not extended sinc e the lower threshold was crossed during the negative slope portion of the dither wave form, the following two dither periods are extended since the low switch point was not crossed during the negative slope portion of the waveform. tle 7241e functional description and electrical characteristics data sheet 39 rev. 1.1, 2009-01-19 figure 20 enhanced dither waveform the extension of the dither period will be terminated when the lower switch threshold is crossed or when the extension time has e xceeded the enhanced dither time out period (minimum 15 ms) - see figure 21 . enhanced dither time out data sheet 40 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 21 enhanced dither time-out tle 7241e functional description and electrical characteristics data sheet 41 rev. 1.1, 2009-01-19 electrical char acteristics 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. 5.5.2.1 outx 3) enhanced dither time out t out(ed) 15 ? 25 ms ? 5.5.2.2 outx dither 3)4) amplitude reg = 04 h i dap-p 40.5 50 60.5 mvpp 50 mv setting programmed ref = 2.5v 5.5.2.3 outx dither 3)4) amplitude reg = 08 h i dap-p 90.9 101 110.9 mvpp 100 mv setting programmed ref = 2.5v 5.5.2.4 outx dither 3)4) amplitude reg = 0c h i dap-p 141.4 151 161.4 mvpp 150 mv setting programmed ref = 2.5v 5.5.2.5 outx dither 3)4) amplitude reg = 10 h i dap-p 191.8 202 211.8 mvpp 200 mv setting programmed ref = 2.5v 5.5.2.6 outx dither 3)4) amplitude reg = 14 h i dap-p 242.3 252 262.3 mvpp 250 mv setting programmed ref = 2.5v 5.5.2.7 outx dither 3)4) amplitude reg = 18 h i dap-p 292.7 303 312.7 mvpp 300 mv setting programmed ref = 2.5v 5.5.2.8 outx dither 3)4) amplitude reg = 1c h i dap-p 343.2 353 363.2 mvpp 350 mv setting programmed ref = 2.5v 5.5.2.9 outx dither frequency reg = 34 h f dither -15% 100 +15% hz 100 hz setting programmed 3) 5.5.2.10 outx dither frequency reg = 23 h f dither -15% 150 +15% hz 150 hz setting programmed 3) 5.5.2.11 outx dither frequency reg = 1a h f dither -15% 200 +15% hz 200 hz setting programmed 3) data sheet 42 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.5.2.12 outx dither frequency reg = 15 h f dither -15% 250 +15% hz 250 hz setting programmed 3) 5.5.2.13 outx dither frequency reg = 11 h f dither -15% 308 +15% hz 300 hz setting programmed 3) 5.5.2.14 outx dither frequency reg = 0f h f dither -15% 350 +15% hz 350 hz setting programmed 3) 5.5.2.15 outx dither frequency reg = 0d h f dither -15% 403 +15% hz 400 hz setting programmed 3) 5.5.2.16 outx dither frequency reg = 0c h f dither -15% 437 +15% hz 450 hz setting programmed 3) 5.5.2.17 outx dither frequency reg = 0a h f dither -15% 524 +15% hz 500 hz setting programmed 3) 1) positive current flow is into the device. 2) t j = 25 c 3) not subject to production test, specified by design 4) when the internal reference is used (ref pin grou nded), the minimum and maximum limits must be increased by +/- 2% electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. tle 7241e functional description and electrical characteristics data sheet 43 rev. 1.1, 2009-01-19 5.5.3 input command out of range / dither clipping if an average current command between 000 h and 029 h inclusive (0 ma and 50 ma with a 1 sense resistor) is received, then the av erage current will be set to 000 (channel disabled) and the cor (command out of range) error bit will be set. the average current set point verification reported in the miso word, however, will be the actual average current command, not 000 h . if an average current co mmand greater than 3d6 h (1.18 a with a 1 sense resistor) is received, then the average current will be set to 3d6 h , and the cor error bit will be set. the average current set point verification reported in the miso word, however, will be the actual commanded current, not 3d6 h . the minimum limit for the lower switch point is 19 h (30 ma with a 1 sense resistor) and the maximum limit for the upper switch point is 3ff h (1.23 a with a 1 sense resistor). if the microprocessor sets the average curr ent command and the switching hysteresis setting to values that result in swit ch points beyond these limits, the tle 7241e will clip the switch point to 19 h or 3ff h and the cor error bit will be set. if the average current set point and the switchin g hysteresis setting do not result in switch points outside the usable range (19 h to 3ff h ), but dither is enabled and the dither amplitude setting results in an out of range switch point, then the dclp fault bit will be set. the fault bit is set when the calculated switch point (average current + hysteresis + dither) exceeds the upper or lower limit, not when the registers are programmed. when the dclp fault bit is set, the tle 7241e will enter ?symmetrical dither clipping? mode within one dither cycle afte r the clipping occurs. during symmetrical dither clipping mode, the device maintains the average current set-point by reducing the amplitude of the dither waveform. up to one full dither cycle may be r equired to exit the ?symmetrical dither clipping mode? and resume norma l operation when the registers are re- programmed. see figure 22 for an example of the dither clipping waveform. data sheet 44 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 22 symmetrical dither clipping 5.5.4 error correction registers / average switch threshold trimming the average switch threshold of each chan nel is trimmed at wafer test under the following operating conditions: t amb = 25 q c, v bat = 14 v, v cc = 5.0 v, v ref = 2.5 v, average current command = 299 h (800 ma with 1 : sense resistor), dither = off, hysteresis = 80 mvpp. the tle 7241e includes 5 error correction registers for each channel. the registers are written during room temperatur e wafer testing. after the device has been trimmed, the average of the upper and lower switch thre sholds is measured at 5 average current operating points. the differ ence in the measured value and the ideal value is permanently stored in the 5 error registers. the contents of the erro r correction register are an 8 bit signed value that must be added to the ideal current command to minimize the average current error. error correction register # corresponding average current register setting (hex) corresponding ideal average current with a 1 : ext. sense resistor 0 0a6 200 ma 1 14d 400 ma 2 1f3 600 ma 3 29a 800 ma 4 340 1000 ma tle 7241e functional description and electrical characteristics data sheet 45 rev. 1.1, 2009-01-19 for example: ? measured average switch threshold at 0a6 h during infineon production test = 207 mv ? ideal average switch threshold at 0a6 h = 199.6 mv ? error correction = -7.4 mv / (1.2 mv/count) = -6 counts ? the contents of the error correction register are -6 or fa h the contents of the error correction regi sters can be used by the application microcontroller to improve the accuracy of the average switch points. in the above example, when the microcontroller requests an average current of 200 ma (assuming a 1 : sense resistor), the command sent should be 0a6 (ideal) - 6 (error correction) = 0a0. for current commands between the 5 measur ed operating points, the microprocessor can use linear (or more complex) interpol ation to calculate the appropriate error correction values. data sheet 46 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.6 spi command and diagnosis structure 5.6.1 spi signal description the spi serial interface has the following features: ? full duplex, 4-wire synchronous communication ? slave mode operation only ? fixed sck polarity and phase requirements ? fixed 16-bit command word sck operation up to 5.0 mhz (the maximum clock frequency may be limited to a value less than 5.0 mhz by the minimum required so setup time of the spi master device and by the total capacitive load on the so bu s node. with a so load capacitance of 200 pf the maximum spi frequency is 3.2 mhz). the tle 7241e ic serial peripheral interface (spi) is used to transmit and receive data synchronously with the master spi device. communication occurs over a full-duplex, four wire spi bus. the tle 7241e ic will operate only as a slave device to the master, and requires four external pins; si, so, sck, and csb. all words are 16 bits long and sent msb first. the device is selected when t he csb signal is asserted (low). the master will then send 16 (or a multiple of 16) clock pulses over the sck pin. the tle 7241e will simultaneously turn on the serial output so and return the miso return bits. when receiving, valid data is latched on the rising edge of each sck pulse. the serial output data is available on the rising edge of sck, and transitions on the falling edge of sck. see figure 23 for spi timing diagram. the number of clock cycles occurring on the pi n sck while the csb pin is asserted low must be 16 or an integer multiple of 16, otherwise the spi mosi data will be ignored. the fault registers are double buffered. the first buffer layer will latch a fault at the time the fault is detect ed. this inner layer buffer is clear ed when the fault condition is no longer present and the fault bit has been communicated to the microprocessor by a miso response. the second layer buffer will la tch the output of the inner layer buffer whenever the csb pin transitions from low to high. the output of this buffer layer is transferred to the miso shift register on e spi frame after the corresponding mosi command has been received from the microcontroller. the miso data word value of ffff h is never generated by the tle 7241e, and will indicate a hi-z state on the so pin when an external pull-up resistor to v dd is used. this feature can be used to detect an open connection between the so pin of the tle 7241 e and the microcontroller. all undefined mosi command words will be ignored by the tle 7241e, and the miso response during the next spi frame will be undefined (but not ffff h ). note: the ol/sg fault bit is latched into the miso register, and then updated within t dly ( 1.7 s) after the rising edge of the csb signal when the received mosi word is an general configuration command. tle 7241e functional description and electrical characteristics data sheet 47 rev. 1.1, 2009-01-19 figure 23 spi timing diagram data sheet 48 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics electrical char acteristics 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. 5.6.1.1 csb input bias current i csb -25 -10 -5 a v csb = 0 v pull-up source is from pin v so 5.6.1.2 si input pull- down current i si 5 10 25 a v si = v vso 5.6.1.3 sck input pull- down current i sck 5 10 25 a v sck = v vso 5.6.1.4 so tri-state leakage current i sot -10 0 10 a csb = 0.7 v dd 0 v < v so < v vso 5.6.1.5 si, sck, csb, default input capacitance c in ? ? 20 pf 0 v < v so < 5.25 v 3) 5.6.1.6 so tri-state output capacitance c sot ? ? 20 pf 0 v < v so < 5.25 v 3) 5.6.1.7 sck serial clock frequency f sck ? ? 3.2 mhz spi clock spi communications tested at c l = 200 pf on the so pin, t su1 = 40 ns 5.6.1.8 sck clock pulse high time t wh 85 ? ? ns f sck = 3.2 mhz, sck = 2 v to 2 v (see figure 23 ) 5.6.1.9 sck clock pulse low time t wl 85 ? ? ns f sck = 3.2 mhz, sck = 0.8 v to 0.8 v (see figure 23 ) tle 7241e functional description and electrical characteristics data sheet 49 rev. 1.1, 2009-01-19 5.6.1.10 so, csb so pin enable/ disable tsoen, tsodis ? ? 80 ns csb = 2.0 v to so = 0.8 v/2.0 v, 10k ext. so pull-up (see figure 23 ) - enable csb = 0.8 v to so hi-z, 10k ext. so pull-up (see figure 23 ) - disable 5.6.1.11 so, sck 3) output data setup time, so to sck rising edge t su1 80 ? ? ns required setup time by microprocessor equivalent to t wl - t valid so = 0.8 v/2.0 v to sck = 0.8 v (see figure 23 ) 5.6.1.12 so, sck 3) output data hold time, so hold after sck rising edge t h1 150 ? ? ns required hold time by microprocessor equivalent to t wh + t valid - t rso /t fso sck = 2.0 v to so = 0.8 v/2.0 v (see figure 23 ) 5.6.1.13 si, sck input data setup time, si to sck rising edge t su2 20 ? ? ns si = 0.8 v/2.0 v to sck = 2.0 v at 3.2 mhz (see figure 23 ) 5.6.1.14 si, sck input data hold time, si hold after sck rising edge t h2 30 ? ? ns sck = 2.0 v to si = 0.8 v/2.0 v at 3.2 mhz (see figure 23 ) 5.6.1.15 so serial output rise/fall time t rso /t fso ? ? 50 ns c ld = 200 pf (see figure 23 ) electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. data sheet 50 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.6.1.16 si, csb, sck serial inputs rise/fall time t rsi /t fsi ? ? 25 ns 3) 5.6.1.17 csb, sck csb falling edge to sck rising edge t lead 100 ? ? ns csb = 0.8 v to sck = 0.8 v (see figure 23 ) 5.6.1.18 csb, sck sck falling edge to csb rising edge t lag 50 ? ? ns sck = 0.8 v to csb = 0.8 v (see figure 23 ) 5.6.1.19 sck, so falling edge sck to so data valid data valid ? ? 80 ns sck = 0.8 v to so data valid, c ld = 200 pf at 3.2 mhz (see figure 23 ) 5.6.1.20 csb 3) sequential transfers xfer delay 1 ? ? s csb = 2.0 v (increasing) to csb = 2.0 v (decreasing). ic will not require more than maximum time stated between communications. 5.6.1.21 sck, csb falling edge of sck to falling edge of csb t sck1 20 ? ? ns sck = 0.8 v to csb = 2.0 v (see figure 23 ) 5.6.1.22 sck, csb rising edge of csb to rising edge of sck t sck2 10 ? ? ns csb = 2.0 v to sck = 0.8 v (see figure 23 ) electrical char acteristics (cont?d) 1) t j = -40 to 150 c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. tle 7241e functional description and electrical characteristics data sheet 51 rev. 1.1, 2009-01-19 figure 24 fault bit refres h delay time ( t dly ) 5.6.1.23 sck number of sck pulses while csb low (n is a positive integer) n sck 16 n u 16 ? pul- ses ? 5.6.1.24 csb 3) miso shift register load delay time t dly ? 1.7 ? p s csb = 2.0 v (increasing) to miso data loaded into shift register (see figure 24 ) latched fault bit csb tdly 1) positive current flow is into the device. 2) t j = 25 q c. 3) not subject to production test, specified by design. electrical char acteristics (cont?d) 1) t j = -40 to 150 q c; v bat = 9 v to 18 v; v dd = 4.75 v to 5.25 v pos. parameter symbol limit values unit test conditions and instructions min. typ. 2) max. data sheet 52 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 5.6.2 spi command structure table 1 spi command summary channel instruction id command type miso response - next csb assertion b15 b14 b13 0 0 0 average current set point - ch#1 average current verification and status - ch#1 0 0 1 dither configuration - ch#1 dither config verification ch#1 0 1 0 general configuration - ch#1 general config verification ch#1 0 1 1 read register - ch#1 register contents - ch#1 1 0 0 average current set point - ch#2 average current verification and status - ch#2 1 0 1 dither configuration - ch#2 dither config verification ch#2 1 1 0 general configuration - ch#2 general config verification ch#2 1 1 1 read register - ch#2 register contents - ch#2 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 channel mosi ch 0 0 x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 miso ch 0 0edgcordclpd9d8d7d6d5d4d3d2d1d0 channel diagnostic error command out of range dither clipping i average average current setpoint i average average current setpoint figure 25 average current set point mosi ? b12 - b10 nu: not used, default = 0 (40 mvpp) ? b9 - b0: average current set point, average current set point setting (see table 2 ), default = 0 (0 ma) tle 7241e functional description and electrical characteristics data sheet 53 rev. 1.1, 2009-01-19 miso ? b12 diagnostic error: = 1 if ol/sg = 1 or vsht = 1 or otmp = 1 (channel specific) ? b11 command out of range: = 1 if the average current set point + the hysteresis setting result in a switch point > 1.23 v or < 0.03 v ? b10 dither clipping: = 1 if the dither setti ng, average current set point, and hysteresis setting result in a switch point > 1.23 v or < 0.03 v ? b9 - b0 average current set point: contents of the average current set point command (non-clipped) table 2 average output current key (typical) - partial table cor hex d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 average switch point [mv] load current with 1 sense resistor [ma] load current with 0.68 sense resistor [ma] 0 000 0 0 0 0 0 0 0 0 0 0 0.00 0.00 0.00 1 001 0 0 0 0 0 0 0 0 0 1 0.00 0.00 0.00 1 002 0 0 0 0 0 0 0 0 1 0 0.00 0.00 0.00 1 003 0 0 0 0 0 0 0 0 1 1 0.00 0.00 0.00 ? 1 028 0 0 0 0 1 0 1 0 0 0 0.00 0.00 0.00 1 029 0 0 0 0 1 0 1 0 0 1 0.00 0.00 0.00 1) 02a 0 0 0 0 1 0 1 0 1 0 50.45 50.45 74.19 1) 02b 0 0 0 0 1 0 1 0 1 1 51.65 51.65 75.96 1) 02c 0 0 0 0 1 0 1 1 0 0 52.85 52.85 77.72 ? 0 0a6 0 0 1 0 1 0 0 1 1 0 199.39 199.39 293.23 ? 0 14d 0 1 0 1 0 0 1 1 0 1 399.99 399.99 588.22 ? 0 1f3 0 1 1 1 1 1 0 0 1 1 599.38 599.38 881.45 ? 0 29a 1 0 1 0 0 1 1 0 1 0 799.98 799.98 1176.44 ? data sheet 54 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics (5) (6) note: when a new average current command or hysteresis setting is received, the new data is loaded immediately with the rising edge of csb (not synchronized with the dither waveform). the dither waveform is not reset when the new average current command or hysteresis setting is received. 0 340 1 1 0 1 0 0 0 0 0 0 999.38 999.38 1469.67 ? 1) 3d3 1 1 1 1 0 1 0 0 1 1 1175.95 1175.95 1729.33 1) 3d4 1 1 1 1 0 1 0 1 0 0 1177.15 1177.15 1731.10 1) 3d5 1 1 1 1 0 1 0 1 0 1 1178.35 1178.35 1732.87 1) 3d6 1 1 1 1 0 1 0 1 1 0 1178.35 1178.35 1732.87 1 3d7 1 1 1 1 0 1 0 1 1 1 1178.35 1178.35 1732.87 ? 1 3fc 1 1 1 1 1 1 1 1 0 0 1178.35 1178.35 1732.87 1 3fd 1 1 1 1 1 1 1 1 0 1 1178.35 1178.35 1732.87 1 3fe 1 1 1 1 1 1 1 1 1 0 1178.35 1178.35 1732.87 1 3ff 1 1 1 1 1 1 1 1 1 1 1178.35 1178.35 1732.87 sp avg register value 2 10 ----------------------------------- - 1230 mv u = i avg register value 2 10 ----------------------------------- - 1230 r sense --------------- - u ma = 1) cor state dependent on the switching hysteresis value. table 2 average output current key (typical) - partial table (cont?d) cor hexd9d8d7d6d5d4d3d2d1d0average switch point [mv] load current with 1 : sense resistor [ma] load current with 0.68 : sense resistor [ma] b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 channel enhanced dither mosi ch 0 1 ed da4 da3 da2 da1 da0 df6 df5 df4 df3 df2 df1 df0 miso ch 0 1 ed da4 da3 da2 da1 da0 df6 df5 df4 df3 df2 df1 df0 channel enhanced dither dither configuration dither configuration dither frequency dither frequency dither amplitude dither amplitude tle 7241e functional description and electrical characteristics data sheet 55 rev. 1.1, 2009-01-19 figure 26 dither programming mosi ? b12 enhanced dither: enables the enhanced dither feature when ed = 1, default = 0 (disabled) ? b11 - b7 dither amplitude: setting for the amplitude of the dither waveform (see table 3 ), default = 00 h (dither disabled) ? b6 - b0 dither frequency: setting for the frequency of the dither waveform (see table 4 ), default = 00 h (dither disabled) note: to disable the dither waveform, both the amplitude and frequency fields must be set to zero. these fields must both be cl eared in the same spi communication frame. programming the frequency to zero when the amplitude is set to a non-zero value will result in incorrect current regulation. miso ? b12 enhanced dither: contents of the ed bit of the dither c onfiguration register ? b11 - b7 dither amplitude: contents of the dither amplitude register (shadow register) ? b6 - b0 dither frequency: contents of the di ther frequency register (shadow register) note: when a dither configuration command is received which changes either the dither frequency or the dither amplitude settings, the new dither waveform characteristics will take effect at the beginning of the next dither period. data sheet 56 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 27 start of dither cycle tle 7241e functional description and electrical characteristics data sheet 57 rev. 1.1, 2009-01-19 table 3 ideal dither amplitude key (typical) hex da4 da3 da2 da1 da0 dither amplitude [mvpp] dither amplitude with 1 sense resistor [mapp] dither amplitude with 0.68 sense resistor [mapp] 00 0 0 0 0 0 0.0 0.00 0.00 01 0 0 0 0 1 12.6 12.6 18.5 02 0 0 0 1 0 25.2 25.2 37.1 03 0 0 0 1 1 37.8 37.8 55.6 04 0 0 1 0 0 50.5 50.45 74.19 05 0 0 1 0 1 63.1 63.06 92.74 06 0 0 1 1 0 75.7 75.68 111.29 07 0 0 1 1 1 88.3 88.29 129.84 08 0 1 0 0 0 100.9 100.90 148.38 09 0 1 0 0 1 113.5 113.51 166.93 0a 0 1 0 1 0 126.1 126.13 185.48 0b 0 1 0 1 1 138.7 138.74 204.03 0c 0 1 1 0 0 151.4 151.35 222.58 0d 0 1 1 0 1 164.0 163.96 241.12 0e 0 1 1 1 0 176.6 176.58 259.67 0f 0 1 1 1 1 189.2 189.19 278.22 10 1 0 0 0 0 201.8 201.80 296.77 11 1 0 0 0 1 214.4 214.41 315.32 12 1 0 0 1 0 227.0 227.03 333.86 13 1 0 0 1 1 239.6 239.64 352.41 14 1 0 1 0 0 252.3 252.25 370.96 15 1 0 1 0 1 264.9 264.86 389.51 16 1 0 1 1 0 277.5 277.48 408.05 17 1 0 1 1 1 290.1 290.09 426.60 18 1 1 0 0 0 302.7 302.70 445.15 19 1 1 0 0 1 315.3 315.32 463.70 1a 1 1 0 1 0 327.9 327.93 482.25 1b 1 1 0 1 1 340.5 340.54 500.79 data sheet 58 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics (7) (8) 1c 1 1 1 0 0 353.2 353.15 519.34 1d 1 1 1 0 1 365.8 365.77 537.89 1e 1 1 1 1 0 378.4 378.38 556.44 1f 1 1 1 1 1 391.0 390.99 574.99 v dithamp register value 10.5 u 2 10 ----------------------------------------------------- - 1230 u mvpp = i dithamp register value 10.5 u 2 10 ----------------------------------------------------- - 1230 r sense --------------- - u mapp = table 4 ideal dither frequency key (typical)- partial table hex df6 df5 df4 df3 df2 df1 df0 dither frequency 00 0 0 0 0 0 0 0 0.0 hz 01 0 0 0 0 0 0 1 5238.1 hz 02 0 0 0 0 0 1 0 2619.0 hz 03 0 0 0 0 0 1 1 1746.0 hz 04 0 0 0 0 1 0 0 1309.5 hz 05 0 0 0 0 1 0 1 1047.6 hz 06 0 0 0 0 1 1 0 873.0 hz 07 0 0 0 0 1 1 1 748.3 hz 08 0 0 0 1 0 0 0 654.8 hz 09 0 0 0 1 0 0 1 582.0 hz 0a 0 0 0 1 0 1 0 523.8 hz 0b 0 0 0 1 0 1 1 476.2 hz 0c 0 0 0 1 1 0 0 436.5 hz 0d 0 0 0 1 1 0 1 402.9 hz 0e 0 0 0 1 1 1 0 374.2 hz 0f 0 0 0 1 1 1 1 349.2 hz table 3 ideal dither am plitude key (typical) hex da4 da3 da2 da1 da0 dither amplitude [mvpp] dither amplitude with 1 : sense resistor [mapp] dither amplitude with 0.68 : sense resistor [mapp] tle 7241e functional description and electrical characteristics data sheet 59 rev. 1.1, 2009-01-19 10 0 0 1 0 0 0 0 327.4 hz 11 0 0 1 0 0 0 1 308.1 hz 12 0 0 1 0 0 1 0 291.0 hz 13 0 0 1 0 0 1 1 275.7 hz 14 0 0 1 0 1 0 0 261.9 hz 15 0 0 1 0 1 0 1 249.4 hz 16 0 0 1 0 1 1 0 238.1 hz 17 0 0 1 0 1 1 1 227.7 hz 18 0 0 1 1 0 0 0 218.3 hz 19 0 0 1 1 0 0 1 209.5 hz 1a 0 0 1 1 0 1 0 201.5 hz 1b 0 0 1 1 0 1 1 194.0 hz 1c 0 0 1 1 1 0 0 187.1 hz 1d 0 0 1 1 1 0 1 180.6 hz 1e 0 0 1 1 1 1 0 174.6 hz 1f 0 0 1 1 1 1 1 169.0 hz 20 0 1 0 0 0 0 0 163.7 hz 21 0 1 0 0 0 0 1 158.7 hz 22 0 1 0 0 0 1 0 154.1 hz 23 0 1 0 0 0 1 1 149.7 hz 24 0 1 0 0 1 0 0 145.5 hz 25 0 1 0 0 1 0 1 141.6 hz 26 0 1 0 0 1 1 0 137.8 hz 27 0 1 0 0 1 1 1 134.3 hz 28 0 1 0 1 0 0 0 131.0 hz 29 0 1 0 1 0 0 1 127.8 hz 2a 0 1 0 1 0 1 0 124.7 hz 2b 0 1 0 1 0 1 1 121.8 hz 2c 0 1 0 1 1 0 0 119.0 hz 2d 0 1 0 1 1 0 1 116.4 hz table 4 ideal dither frequency key (typical)- partial table (cont?d) hex df6 df5 df4 df3 df2 df1 df0 dither frequency data sheet 60 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics 2e 0 1 0 1 1 1 0 113.9 hz 2f 0 1 0 1 1 1 1 111.4 hz 30 0 1 1 0 0 0 0 109.1 hz 31 0 1 1 0 0 0 1 106.9 hz 32 0 1 1 0 0 1 0 104.8 hz 33 0 1 1 0 0 1 1 102.7 hz 34 0 1 1 0 1 0 0 100.7 hz 35 0 1 1 0 1 0 1 98.8 hz 36 0 1 1 0 1 1 0 97.0 hz 37 0 1 1 0 1 1 1 95.2 hz 38 0 1 1 1 0 0 0 93.5 hz 39 0 1 1 1 0 0 1 91.9 hz 3a 0 1 1 1 0 1 0 90.3 hz 3b 0 1 1 1 0 1 1 88.8 hz 3c 0 1 1 1 1 0 0 87.3 hz 3d 0 1 1 1 1 0 1 85.9 hz 3e 0 1 1 1 1 1 0 84.5 hz 3f 0 1 1 1 1 1 1 83.1 hz 40 1 0 0 0 0 0 0 81.8 hz 41 1 0 0 0 0 0 1 80.6 hz 42 1 0 0 0 0 1 0 79.4 hz 43 1 0 0 0 0 1 1 78.2 hz 44 1 0 0 0 1 0 0 77.0 hz 45 1 0 0 0 1 0 1 75.9 hz 46 1 0 0 0 1 1 0 74.8 hz 47 1 0 0 0 1 1 1 73.8 hz 48 1 0 0 1 0 0 0 72.8 hz 49 1 0 0 1 0 0 1 71.8 hz 4a 1 0 0 1 0 1 0 70.8 hz 4b 1 0 0 1 0 1 1 69.8 hz table 4 ideal dither frequency key (typical)- partial table (cont?d) hex df6 df5 df4 df3 df2 df1 df0 dither frequency tle 7241e functional description and electrical characteristics data sheet 61 rev. 1.1, 2009-01-19 4c 1 0 0 1 1 0 0 68.9 hz 4d 1 0 0 1 1 0 1 68.0 hz 4e 1 0 0 1 1 1 0 67.2 hz 4f 1 0 0 1 1 1 1 66.3 hz 50 1 0 1 0 0 0 0 65.5 hz 51 1 0 1 0 0 0 1 64.7 hz 52 1 0 1 0 0 1 0 63.9 hz 53 1 0 1 0 0 1 1 63.1 hz 54 1 0 1 0 1 0 0 62.4 hz 55 1 0 1 0 1 0 1 61.6 hz 56 1 0 1 0 1 1 0 60.9 hz 57 1 0 1 0 1 1 1 60.2 hz 58 1 0 1 1 0 0 0 59.5 hz 59 1 0 1 1 0 0 1 58.9 hz 5a 1 0 1 1 0 1 0 58.2 hz 5b 1 0 1 1 0 1 1 57.6 hz 5c 1 0 1 1 1 0 0 56.9 hz 5d 1 0 1 1 1 0 1 56.3 hz 5e 1 0 1 1 1 1 0 55.7 hz 5f 1 0 1 1 1 1 1 55.1 hz 60 1 1 0 0 0 0 0 54.6 hz 61 1 1 0 0 0 0 1 54.0 hz 62 1 1 0 0 0 1 0 53.5 hz 63 1 1 0 0 0 1 1 52.9 hz 64 1 1 0 0 1 0 0 52.4 hz 65 1 1 0 0 1 0 1 51.9 hz 66 1 1 0 0 1 1 0 51.4 hz 67 1 1 0 0 1 1 1 50.9 hz 68 1 1 0 1 0 0 0 50.4 hz 69 1 1 0 1 0 0 1 49.9 hz table 4 ideal dither frequency key (typical)- partial table (cont?d) hex df6 df5 df4 df3 df2 df1 df0 dither frequency data sheet 62 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics (9) 6a 1 1 0 1 0 1 0 49.4 hz 6b 1 1 0 1 0 1 1 49.0 hz 6c 1 1 0 1 1 0 0 48.5 hz 6d 1 1 0 1 1 0 1 48.1 hz 6e 1 1 0 1 1 1 0 47.6 hz 6f 1 1 0 1 1 1 1 47.2 hz 70 1 1 1 0 0 0 0 46.8 hz 71 1 1 1 0 0 0 1 46.4 hz 72 1 1 1 0 0 1 0 45.9 hz 73 1 1 1 0 0 1 1 45.5 hz 74 1 1 1 0 1 0 0 45.2 hz 75 1 1 1 0 1 0 1 44.8 hz 76 1 1 1 0 1 1 0 44.4 hz 77 1 1 1 0 1 1 1 44.0 hz 78 1 1 1 1 0 0 0 43.7 hz 79 1 1 1 1 0 0 1 43.3 hz 7a 1 1 1 1 0 1 0 42.9 hz 7b 1 1 1 1 0 1 1 42.6 hz 7c 1 1 1 1 1 0 0 42.2 hz 7d 1 1 1 1 1 0 1 41.9 hz 7e 1 1 1 1 1 1 0 41.6 hz 7f 1 1 1 1 1 1 1 41.2 hz f dith 1.76 10 6 u register value 336 u --------------------------------------------------- - hz = table 4 ideal dither frequency key (typical)- partial table (cont?d) hex df6 df5 df4 df3 df2 df1 df0 dither frequency b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 channel fault typing current source mosi ch1 0 xxxxxxxftsr1sr0sw2sw1sw0 miso ch 1 0 ol/sg vsht otmp 0 0 0 ref ft sr1 sr0 sw2 sw1 sw0 channel open load or short to gnd short to vpwr over temperature ext./int. reference volt. fault typing current source switching hysteresis slew rate slew rate general configuration general configuration switching hysteresis tle 7241e functional description and electrical characteristics data sheet 63 rev. 1.1, 2009-01-19 figure 28 general configuration register mosi ? b12 - b6: not used, ignored - don?t care ? b5 fault typing bit: activates a 40 p a pull-up current on posx pin for sg/ol differentiation. default = 0 (disabled) ? b4 - b3 slew rate: setting for the slew rate (see table 5 ). default = 3 (1.2 v/ p s) ? b2 - b0 switching hysteresis: setting for the hysteresis value (see table 6 ), default = 0 (40 mvpp) miso ? b12 ol/sg: open load / short to ground fault flag ? b11 vsht: short to bat (shorted load) fault flag ? b10 otmp: overtemperature fault flag ? b9 - b7: not used, always 0 ? b6 ref: = 0 when an external reference is detected on the ref pin, b6 ref: = 1 when the ref pin is grounded and the internal 2.5 v reference is active ? b5 ft: contents of the ft-bit in the general configuration register ? b4 - b3 slew rate: contents of the slew rate settings in the general configuration register ? b2 - b0 sw: contents of the switching hyster esis setting in the general configuration register table 5 slew rate control key sr1 sr0 t f /t r (4 v - 10 v) slew rate 0 0 0.5 p s 12 v/ p s 0 1 1 p s 6 v/ p s 1 0 2 p s 3 v/ p s 1 1 5 p s 1.2 v/ p s table 6 switching hysteresis key sh2 sh1 sh0 hysteresis 0 0 0 40 mvpp 0 0 1 50 mvpp 0 1 0 60 mvpp 0 1 1 70 mvpp 1 0 0 80 mvpp 1 0 1 90 mvpp 1 1 0 100 mvpp 1 1 1 110 mvpp b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 channel mosi ch1 1 0 0rid2rid1rid0xxxxxxxx miso ch 1 1 0 0 rid2 rid1 rid0 rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 channel read error registers read error registers register id register value register id command extension command extension data sheet 64 rev. 1.1, 2009-01-19 tle 7241e functional description and electrical characteristics figure 29 read error register mosi ? b12 - b11 command extension: always send as 00 ? b10 - b8 register id: selects register to be transmitted to p p during next spi frame (see table 7 ) ? b7 - b0: not used, ignored / don't care tle 7241e functional description and electrical characteristics data sheet 65 rev. 1.1, 2009-01-19 miso ? b12 - 11 command extension: always 00 ? b10 - b8 rid0-2: register id of the register contents in b7 - b0 ? b7 - b0 rv: register contents table 7 error register values per channel rid2 rid1 rid0 register name 0 0 0 error correction - 200 mv 0 0 1 error correction - 400 mv 0 1 0 error correction - 600 mv 0 1 1 error correction - 800 mv 1 0 0 error correction - 1000 mv 1 0 1 chip revision code 1 1 0 00 h 1 1 1 00 h the mosi commands ?x1101xxx xxxxxxxx?, ?x1110xxx xxxxxxxx?, and ?x1111xxx xxxxxxxx? are not valid comm ands for the tle7241 e. the miso return words associated with these commands are undefined, but exclude the word ?ffff h ?. data sheet 66 rev. 1.1, 2009-01-19 tle 7241e application 6 application tle7241 bat gnd neg1 out1 pos1 default vso si so sck vdd ref neg2 out2 pos2 csb rsns1 vpwr/ recirc cbat cref cng1 (3) cps1 (3) csol1 cvdd sol1 vpwr +5v 2.5v ref rsns2 vpwr/ recirc cng2 (3) cps2 (3) cout2 (3) csol2 sol2 cout1(3) cso +5v or 3.3v p controller tri-core tc17xx rso (5) test pgnd1 pgnd2 rbat (2) (4) rdft (1). figure 30 application circuit note: this is a very simplified example of an application circuit. the function must be verified in the real application 1. recommended for applications with microcontroller i/o voltage levels less than 5.0 v. the resistor will limit the microcontroll er input current when the adjacent pins default and v dd are shorted together. 2. required for applications that do not provide a reverse battery protected bat supply. r bat may also be required to limit the bat pin current during bat voltage transient events (e. g. iso pulses). 3. may be required for module level complian ce with emc specific ations, but they are not required for tle7241 functionality or stability. 4. connect to the ref pin directly to gnd to enable the internal 2.5 v voltage reference. 5. optional. defines so signal voltage when the so pin has failed as an open circuit. note: in case of an unused channel, the outx, negx, and posx pins should be connected together. tle 7241e application data sheet 67 rev. 1.1, 2009-01-19 6.1 layout notes ? the pos pin should be connected directly to the external sense resistor with a dedicated trace. ? the neg pin should be connected directly to the external s ense resistor with a dedicated trace. ? the pos pin trace should be routed near the neg pin trace and both traces should not be routed near noise inducing signal lines and/or components (spi clock signals, switching power supply inductors, etc.). ? for best accuracy, the external sense resistor should be placed near the ic. ? a capacitor should be connected between the v dd pin and ground near the ic. ? a capacitor should be connected between the v so pin and ground near the ic. ? a capacitor should be connected between the bat pin and ground near the ic. ? a capacitor should be connected between the ref pin and ground near the ic. ? the exposed lead frame should be connected to a large area ground plane and to the pins pgnd1, pgnd2. ? the gnd pin should be connected directly to the ground plane. data sheet 68 rev. 1.1, 2009-01-19 tle 7241e package outlines 7 package outlines exposed diepad index marking 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion of 0.05 max. per side index marking ejector mark ejector mark 1 10 10 5.2 1 20 11 4.6 bottom view 11 20 1.27 0.08 0.4 2) a-b 0.25 m 20x cd 20x c c 0.1 0...0.10 -0.2 2.45 2.6 max. -0.2 7.6 1) 0.35 x 45 0.7 0.2 10.3 0.3 +0.09 0.23 8 max. a d 1) 12.8 -0.2 b pg-dso-20-27-po v14 figure 31 pg-dso-20-27 edp (plastic dual small outline exposed die pad) you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in m m green product (rohs-compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with go vernment regulations the device is available as a green product. green prod ucts are rohs-compliant (i.e pb-free finish on leads and suitable for pb-f ree soldering according to ipc/jedec j- std-020). tle 7241e revision history data sheet 69 rev. 1.1, 2009-01-19 8 revision history version date changes rev. 1.1 2009-01-19 p a ge 6 8 : upd a ted p a ck a ge dr a wing ( s t a nd-off) p a ge 69-70: a dded revi s ion hi s tory, u pd a ted leg a l di s cl a imer edition 2009-01-19 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respec t to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com published by infineon technologies ag |
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